1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a dummy pattern arrangement method, and more particularly to a semiconductor integrated circuit device including a functional circuit region and a dummy region, and a dummy pattern arrangement method.
2. Description of Related Art
From past to now, in a manufacturing process of a semiconductor integrated circuit device, CMP (Chemical Mechanical Polishing) has been used to planarize a buried insulating film for STI (Shallow Trench Isolation), an interlayer insulating film, or the like.
To explain the CMP, surface flatness of an object to be polished reduces due to its pattern density after polishing. That is, the surface flatness is high in a region with a high base pattern density and is low in a region with a low base pattern density. This is because dishing occurs in the density with a low base pattern density. If the insulating film is too polished due to dishing, the following problem arises. That is, pattern short-circuiting occurs upon processing a metal layer overlying the insulating film. To that end, dummy patterns, which do not electrically function, are arranged in the region with a low base pattern density in order to avoid dishing regarding CMP.
FIG. 9 is a plan view of a conventional semiconductor integrated circuit device having dummy patterns. FIG. 10 is a sectional view taken along the line 10A-10A of FIG. 9. As shown in FIGS. 9 and 10, a conventional semiconductor integrated circuit device 900 includes functional circuit regions 920 (920a and 920b) and a dummy region 910. The dummy region 910 is sandwiched between the functional circuit regions 920.
The functional circuit region 920a is formed in a region 941 of a semiconductor substrate 931, which has no well formed on a main surface of the substrate. In other words, the functional circuit region 920a is positioned at the left side of a well separation line 901 as viewed from the front. The functional circuit region 920b is formed in a region 942 having a well 932 formed on the main surface of the semiconductor substrate 931. In other words, the functional circuit region 920b is positioned at the right side of a well separation line 901 as viewed from the front.
MOSFETs 921 (921a and 921b) are formed in the functional circuit regions 920 (920a and 920b). The MOSFET 921 has gate electrodes 923 (923a and 923b) on source/drain diffusion layers 922 (922a and 922b). Contact diffusion layers 924 (sub-contact diffusion layer 924a and well contact diffusion layer 924b) are formed around the MOSFETs 921.
In the dummy region 910, plural square dummy gate electrodes 911 and dummy diffusion layers 912 are arranged. The dummy diffusion layers 912 are formed together with the source/drain diffusion layers 922 and the contact diffusion layers 924 of the functional circuit regions 920. The dummy gate electrodes 911 are formed together with the gate electrodes 923 of the functional circuit regions 920.
A buried insulating film 934 separates the MOSFETs in the functional circuit regions 920 from one another. Likewise, a buried insulating film 934 separates dummy patterns in the dummy region 910 from one another. Further, the main surface of the semiconductor substrate 931 is covered with an interlayer insulating film 933.
FIG. 11 shows an example of a data rate of dummy patterns in the conventional semiconductor integrated circuit device. The term data rate refers to a data density or area density of the patterns in a predetermined region or predetermined section (predetermined unit region).
Assuming that each dummy diffusion layer 912 is 1 μm×1 μm, and a pitch between the dummy diffusion layers is 1.6 μm×1.6 μm, a data rate is about 39% {(1×1)/(1.6×1.6)=39%}. Assuming that each dummy gate electrode 911 is 1.4 μm×1.4 μm, and a pitch between the gate electrodes is 1.9 μm×1.9 μm, a data rate is about 54% {(1.4×1.4)/(1.9×1.9)=about 54%}.
In the conventional semiconductor integrated circuit device 900, the dummy diffusion layers 912 are arranged in lattice. The flatness of the buried insulating film 934 in the dummy region 910 is thereby improved. Further, the dummy gate electrodes 911 are arranged in lattice. The flatness of the interlayer insulating film 933 in the dummy region 910 is thereby improved.
As the conventional semiconductor integrated circuit device having dummy patterns, a device disclosed in Japanese Unexamined Patent Publication No. 2002-190516 has been known. In the device disclosed in Japanese Unexamined Patent Publication No. 2002-190516, dummy patterns are electrically connected as a countermeasure against noises. However, a data rate of the dummy patterns is not considered.
By the way, a data rate of a dummy diffusion layer as dummy patterns and a data rate of a dummy gate electrode as dummy patterns are separately set in the conventional semiconductor integrated circuit device. That is, upon designing dummy patterns with CAD tools, only patterns for a dummy diffusion layer are automatically arranged to satisfy data rate of the dummy diffusion layer, and only patterns for a dummy gate electrode are automatically arranged to satisfy data rate of the dummy gate electrode.
In the case where the data rate of the diffusion layer and the data rate of the gate electrode are separately determined in this way, the degree of freedom of arrangement of dummy diffusion layer patterns or gate electrode patterns is lowered upon connecting dummy patterns electrically, or a data rate of a predetermined region is changed and reduced. This causes such problem that in the case of connecting dummy patterns electrically, a desired effect or beneficial effect of dummy patterns cannot be obtained in a CMP step.